NANO3D SYSTEMS, LLC (NANO3D) formulates, markets and sells specialty chemicals for metal deposition including Electroplating (EP), Electroless Plating (ELP), Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD). Our products are used for research and development as well as commercial scale applications, especially in microelectronic, transportation and chemical industries. We also provide custom formulations of plating solutions, precursor synthesis, micro-fabrication and characterization services.
NANO3D launched the new webpage – Product Resources containing an interactive periodic table with information on properties, electrochemical deposition solutions and applications for 83 elements as well as information on electroplating and electroless plating processes. 38 metals & compounds can be deposited using electrochemical products available online at our STORE (EP Au, Cu, Cr, Ni, NiFe, NiCo, Pd, Sn, ELP AgW, Au, Cu, Sn, Zn, CuZn, CoWP, NiP, NiWP, CoWBP as well as plateable TiOx/Pd photoresist, EL Ni kits, Cu plated graphite & Si particles, CNT solutions, Ni & NiFe & Pd foils, reducing agents, plating additives et al). There are 10 metals including Ir, Pd, Pt, Ru, Rh, Au, Ag, Co, Ni, Cu that can be deposited using ALD & CVD precursors supplied by NANO3D in collaboration with our partner.
Advanced Packaging and Scaling
The electrochemical deposition (ECD) equipment and materials market for advanced IC packaging is heating up as 2.5D (silicon, organic and glass interposers), 3D (through-silicon vias, TSV) and fan-out (wafer-level and panel-level processes) technologies begin to ramp up. Heterogeneous multi-chip packaging and fan-out packaging processes enable semiconductor companies to achieve performance goals without just shrinking feature sizes.
Plating for advanced packaging includes Cu & SnAg & Ni pillars with down to 10-30 µm pitch and Cu redistribution layers (RDL) for flip chip technology as well as through-substrate via (hole) filling and Cu RDL’s for 2.5D interposers and 3D-ICs.
Plated mega-Cu pillars (~200 µm thick) and Cu RDL are used for fan-out packages. The latest high-density fan-out packages are migrating toward the 1 µm line/space and beyond. Redistribution layers with smaller critical dimensions enable reducing the total number of redistribution process levels in a fan-out package. At these critical dimensions (CDs), fan-outs will provide better performance and cost. Thickness uniformity, high plating speed with current densities in the range of 400 – 600 mA/cm2, and low stress of Cu electrodeposits are very important for advanced packaging.
Scaling continues to be a vibrant part of the IC business. TSMC is reporting that 25% of their revenue is coming from 7 nm, and 5 nm risk wafers with EUVL up to 14 layers and interconnect pitch of below 30 nm are starting this year or early next year. It’s unclear if copper can extend to 3nm, so the industry is exploring other metals such as cobalt et al. Intel moved from traditional Cu to Co materials for two of the interconnect layers at 10 nm. W plugs at contact level are being replaced with Co fill process.
Defect-free filling of sub-15 nm damascene features (trenches and vias), low electrical resistivity and high electromigration resistance are very important for scaling of on-chip interconnects.