ELECTROCHEMICAL DEPOSITION FOR ADVANCED CHIP PACKAGING
NANO3D’S PLATING TECHNOLOGY FOR 2.5D/3D HIGH DENSITY INTERCONNECTS
Electrochemical deposition processes for 2.5D/3D interconnects developed at NANO3D SYSTEMS LLC offer superior performance and substantially lower cost compared to conventional processes. NANO3D’s processes are based on novel electrochemical nano-materials such as plating solutions with self-assembled suppression-based organic additives to achieve void-free bottom up gap fill and conformal electroless nickel (cobalt) alloys barrier & copper seed layers. These plating solutions enable high speed copper (> 4 μm/min) plating of bumps, pillars and redistribution layers as well as defect-free fill of high aspect ratios (>20) through-substrate vias (TSuVs) with Cu or other metals. Our electrochemical deposition techniques have no limitations on chip design rules and can be applied to all types of 2.5D/3D applications from logic and memory to MEMS, wireless and power electronics. NANO3D’s electrochemical TSuV metallization is fully compatible with all process steps in various 3D TSuV manufacturing schemes currently under evaluation and can be easily incorporated into any finally standardized “process flow of reference”. This low cost electrochemical TSuV technology addresses the major threats for adoption of 2.5D/3D TSuV including scalability to high aspect ratio and high cost. Another threat for adoption of 2.5D/3D TSuV technology, that is related to power density limitation and thermal dissipation from thinned dies, is expected to be solved by using controlled expansion metal alloys (NANO3D’s electroplated INVAR).
ADVANCED CHIP PACKAGING TRENDS
Advanced chip (2.5D/3D) packaging is driven by smart phones (43% of wafer starts) and tablets (13% WS). Advanced packaging is a frenetic market with a growing number of new options. Several advanced packaging types are in the market, such as 2.5D/3D and fan-out. Both types are moving toward more functions and I/Os, supporting larger and more complex dies. In one example of fan-out, a DRAM die is stacked on a logic chip in a package. This brings the memory closer to the logic, enabling more bandwidth. Fan-out packages consist of dies and redistribution layers (RDLs). RDLs are the copper metal interconnects that electrically connect one part of the package to another. Besides 2.5D and fan-out, advanced chip packaging options include 3D-ICs, chipsets, multi-chip modules (MCMs) and system-in-package (SiP). In advanced chip packages, the dies are stacked and connected using copper TSuVs, microbumps and pillars. Copper bumps/pillars/RDLs/TSuVs provide small, fast electrical connections between different devices.
NANO3D’s electrochemical technology enables fine pitches, high aspect ratios, better reliability and lower cost 2.5D/3D interconnects including copper and INVAR TSuVs, bumps, pillars, RDLs et al. Val Dubin, Founder and President of NANO3D SYSTEMS LLC, will make a presentation titled “Electrochemical Deposition of 3D Interconnects” at PRiME 2020 meeting on October 8, 2020 where he will discuss NANO3D’s electrochemical deposition technology for advanced chip packaging.